3D VNWFET-Based Standard Cell Library

The vertical nanowire field effect transistor (VNWFET) is an emerging technology that promises to improve the sustainability of future transistor scaling beyond the limitations of conventional lateral devices. With its 3D gate-all-around (GAA) architecture, such a technology enables designs with improved energy-efficiency as well as reduced footprint and thus interconnect capacitance.   In this context, we use an accurate executable compact model implemented in Verilog-A with a parameter set fitted to measurements of an experimental fabricated VNWFET device to propose a novel flow toward the generation and verification of standard cell libraries. Our work goes from transistor level design and characterization of basic logic cells up to physical design, verification and parasitic extraction. This then allowed us to generate standard cell libraries based on this VNWFET technology.  This dataset includes the outcome of this flow presented by the liberty file of standracd cell libraires based on 3D VNWFET devices while including the resitance and capacitance parasitic for the characterization of the cells. The files correspond to two threshold voltages: Regular (RVT) and Low (LVT) and composed of the following cells: BUFX1_CStatic_JL1 INVX1_CStatic_JL1 NAND2X1_CStatic_JL1 NOR2X1_CStatic_JL1 XOR2X1_CStatic_JL1 Asynch_DFFX1_CStatic_JL1 where the formalism OPnXk_Style_Technology  indicates the Boolean operation OP, the number of inputs n and the drive strength k (k=1 corresponds to 4 NWs per device), as well as the logic design style (i.e., Complementary static logic obtained by using n- and p-type VNWFET) and the technology variant used to implement the cells: Junction-Less Nanowire (JL1). In this data set, we only provide the physical layout (in GDSII format) of the logic cells present in the generated liberty files however, cells with different drive strengths can be provided upon request.